Meta is hiring a Design Verification Engineer - Machine Learning Accelerators!

Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR) and Smart Devices. Compute power requirements of these devices require custom silicon. Meta's Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day.

As a Design Verification Engineer at Meta's Reality Labs, you will work with a multidisciplinary group of researchers and engineers, and use your digital design and verification skills to implement the testing infrastructure to validate new core IP implementations and contribute to development and optimization of state-of-the-art machine learning algorithms.

Responsibilities

• Work with cross-functional leads (product managers, systems architects, researchers, software architects) to develop industry-leading Machine Learning IPs optimized for Mixed Reality and Smart Devices, defining verification methodologies for each core IP.
• Define, track, and lead execution of detailed test plans for modules and top levels.
• Implement scalable test benches including checkers, reference models, assertions in SystemVerilog.
• Drive Design Verification to closure based on functional and code coverage metrics.
• Collaborate with Design, Model, Emulation and Silicon validation teams to ensure design quality across pre- and post-Silicon lifecycle.
• Support hand-off and integration of subsystems/IP blocks into larger SOC environments.

Minimum Qualifications

• 10+ years hands-on experience in SystemVerilog/UVM methodology and C/C++ based verification.
• 10+ years in IP/sub-system and/or SoC level verification (SystemVerilog UVM/OVM).
• Experience in SV Assertions, Formal, or Emulation; EDA tools and scripting (Python, TCL, Perl, Shell).
• Track record of 'first-pass success' in ASIC development cycles.
• Bachelor's degree in Computer Science, Computer Engineering, or equivalent.

Preferred Qualifications

• Masters in EE or CS; 5+ years DV of ML applications/accelerators; SW/HW co-design; low power design; numerical compute verification; FPGA/emulation debug.

Location: Sunnyvale, CA. Compensation: $178,000/year to $250,000/year + bonus + equity + benefits.